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Questions tagged [cpu-pipelines]

124 questions
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What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up the stalled thread?
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Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather than fetch delay. In the instruction pipeline,…
user123
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When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different stages of the pipeline (ie, the initial instruction…
Matt
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Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, then a cache miss occurs, necessitating a fetch from…
SQLSavant
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Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: arithmetic & logic: IF, OF, EX, WB load: IF, OF, EX, MA, WB store: IF, OF, EX, MA branch:…
Stanley Fox
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RISC machines have register renaming?

I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming? I know that Superscalar processors have register renaming, but a…
Pedro Gordo
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Does register renaming remove all kinds of WAR hazard?

For the following two instruction [Note: MOV Destination, Source ] i1 : MOV R1, R2 i2 : ADD R2, R3 Since i1 is reading from R2 and i2 is writing to R2 there is a WAR data dependency and by register renaming like below we can remove this hazard i1…
vikkyhacks
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Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 ... )?

Consider a four stage pipeline, and each stage has delays D1, D2, D3 and D4, so the total delay because of the various stages should be N * (D1 + D2 + D3 + D4) where N is the number of instructions, but I see that this is not the case, I see here…
vikkyhacks
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How efficient is register renaming?

As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's previous value is overwritten, and then map the…
Narrateur du chaos
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Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working with a 5 stages pipeline processor withouth data…
apcarry
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Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): Here, we assume a RISC processor. The text says:…
Gokul
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CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to access something the previous memory instruction…
Rajat
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What's the difference between dynamic and static pipelines?

I was trying to understand what a reservation table is in the context of pipelining, when I found this reference here, where the author mentions that there are static and dynamic pipelines. According to him/her, There are two types of pipelines:…
Humberto Fioravante Ferro
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Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a pipeline. Is it the number of stages of the…
Pieter Verschaffelt
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Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case Execution Time (WCET) analysis. I have gathered a…
tod
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