A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.
Questions tagged [cpu-cache]
252 questions
67
votes
2 answers
What happens to the cache contents on a context switch?
In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache?
Is the behaviour dependent on the architecture or is it a general behaviour followed by all chip manufacturers?
Ankit
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38
votes
2 answers
Are generational garbage collectors inherently cache-friendly?
A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) frequently and collecting old garbage infrequently…
Gilles 'SO- stop being evil'
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28
votes
3 answers
What does the processor do while waiting for a main memory fetch
Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed?
I heard about the idea of switching to another thread, if so what is used to wake up the stalled thread?
102948239408
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25
votes
1 answer
Memory Consistency vs Cache Coherence
Is it true that Sequential Consistency is a stronger property than Cache Coherence?
According to
Sorin, Daniel J; Hill, Mark D; Wood, David A: A Primer on Memory Consistency and Cache Coherence, Morgan & Claypool, 2011
sequential consistency can…
Ayrat
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24
votes
5 answers
How to calculate the number of tag, index and offset bits of different caches?
Specifically:
1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address?
2) Same question as 1) but for fully associative cache?
Correct…
compski
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19
votes
3 answers
Parallelising random reads seems to work well — why?
Consider the following very simple computer program:
for i = 1 to n:
y[i] = x[p[i]]
Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an $n$-element array of words. Here $n$ is large, e.g., $n = 2^{31}$ (so that only a negligible…
Jukka Suomela
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15
votes
1 answer
How does a TLB and data cache work?
I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work.
I understand that the TLB is essentially a cache of most recently used physical addresses. However, I was looking at a diagram in my textbook (shown…
audiFanatic
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14
votes
1 answer
Research on evaluating the performance of cache-obliviousness in practice
Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as well.
The paper by Frigo et al. present some…
Juho
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11
votes
3 answers
CPU Cache is managed by which software component?
CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and then manages (i.e store the data in) cache, using…
gpuguy
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10
votes
2 answers
Cache Direct Map (Index, tag, hit/miss)
Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which says:
Below is a list of 32-bit memory address…
GiH
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9
votes
2 answers
Does the aliasing problem show up in a virtually indexed physically tagged cache?
Basically, and as a simple method, we can access cache with Physical Address which is from the TLB.
But, as another method, we can access cache with Virtual Address. But, in this case, if the cache is not fully flushed between context switch(other…
A.Cho
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9
votes
1 answer
Why is quiescent consistency compositional, but sequential consistency is not
I'm having trouble in comparing these two memory consistency models.
Essentially for sequential consistency I think of real code like this:
int x, y;
void ThreadA()
{
x = 20; //Write
int a = y; //Read
}
void ThreadB()
{
y = 20;
int…
William
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8
votes
3 answers
Write Serialization for Cache Coherence in the presence of Store Buffers
One of the requirements for a coherent memory system is write serialization - "two writes to address X by any two processors are observed in the same order by all processors". I am not sure how this condition would be met when the CPU cores have a…
vln3
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7
votes
1 answer
Tag, index and offset of associative cache
My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given $3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253$ to try to…
GiH
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6
votes
1 answer
How does cache partitioning prevent covert/side-channel attacks?
In a report on an open-source separation kernel (Muen kernel) I was reading,
in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks.
It is mentioned that
In a second step each subject is…
nj2237
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