Computer Science Stack Exchange
Computer Science Stack Exchange

Questions tagged [mips]

48 questions
12
votes
4 answers

Are there competitions for integer programming?

Are there competitions for integer programming like there are for SAT and MAXSAT?
Omar Shehab
  • 326
  • 1
  • 10
3
votes
1 answer

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to access something the previous memory instruction…
Rajat
  • 81
  • 1
  • 4
3
votes
3 answers

Predication execution

I was studying branch prediction & predication execution and faced a trouble.. I'm not quite sure whether I understood the concept of predication but based on what I have learned it is taking both taken and not taken at the same time. For example,…
kyung sub Song
  • 41
  • 2
  • 6
3
votes
1 answer

Patterson & Hennessy, Computer Organization and Design, 5th edition, Question for Ex. 2.3

I am stumbling over the Exercise 2.3 of Chapter 2, i.e.: For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s_0$, $s_1$, $s_2$, $s_3$, and $s_4$,…
lordsnyder
  • 33
  • 3
3
votes
1 answer

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is i3 on i2. Is this correct? I also don't know how…
User9123
  • 31
  • 1
2
votes
0 answers

Why do processor designers allow some pipeline hazards to occure

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so it may be better to allow them than preventing…
Promod Sampath Elvitigala
  • 21
  • 1
2
votes
1 answer

Calculate the CPI of a program

foo: addi $t0,$zero,1 addi $v0,$zero,0 outer: beq $t0,$zero,exitout sll $t0,$t0,0 addi $t1,$zero,0 add $t2,$zero,$a0 addi $t0,$zero,0 inner: addi $t8,$a1,-1 slt $t9,$t1,$t8 beq $t9,$zero,outer sll $t0,$t0,0 addi $v0,$v0,1 lw $t8,0($t2) lw…
First_1st
  • 31
  • 2
2
votes
1 answer

Data hazard in MIPS: SW after ADD

Use the five-stage pipeline with forwarding unit. add $t1, $t2, $t3 sw $t1, 0($t4) In the above code, is the data hazard of t1 fixed by forwarding the correct t1 value from MEM stage to EXE stage? Also, are there totally four forwarding paths,…
samli50801
  • 21
  • 2
2
votes
0 answers

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7, R5, R6}…
Abhishek Ghosh
  • 1,184
  • 9
  • 24
1
vote
2 answers

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: lw $6, -16($6) sw $6, -16($5) So the sw wants the data that comes from the MEM read and it…
Ofek .T.
  • 111
  • 5
1
vote
1 answer

How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw $a0, 8000hex(\$gp) Apparently 0x8000 in binary is 1000…
kanayt
  • 153
  • 5
1
vote
1 answer

Byte/word addressing

I am confused on byte addressable/word addressable architecture. I have studied MIPS implementation and I came to know that when the data is retrieved from main memory, it is shifted accordingly to convert it into a byte. But if this is the case,…
Rajat
  • 81
  • 1
  • 4
1
vote
1 answer

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents to the very next stage, so how does NOPs prevent…
Rajat
  • 81
  • 1
  • 4
1
vote
1 answer

How do I calculate Instruction Per Clock?

Hi! I faced a problem with calculating IPC. I can tell the answers were derived from IPC=instruction/number of cycles. But I have no idea why it has to be calculated that way. Just to understand the meaning of IPC, it seems like how many…
kyung sub Song
  • 41
  • 2
  • 6
1
vote
0 answers

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: 01: ADDI $1, $0, 1000 02: LW $2, 0($1) 03: BEQ $0, $0, LABEL 04: MULT $3, $2 05: ADDI $2, $2, 1000 LABEL: 06: MFLO $4 07: ADDI $2, $1, 5 08: SW $2, 0($1) 09: NOP with: -…
HaiLe
  • 11
  • 2
1
2 3 4