Questions tagged [cache]
40 questions
5
votes
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What does "associative" exactly mean in "n-way set-associative cache"?
I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of associativity, i.e., how many cache lines a set can hold.
If I take associative to mean…
adder
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How does a TLB lookup compare all keys simultaneously?
I am reading OS Concepts dinosaur book which says, "Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared with all keys simultaneously."
I checked How…
mLstudent33
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4
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How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?
In my OS course, the instructor mentioned the following: In UNIX if a parent process creates a new child ("fork") then the child is an exact duplicate of the parent. This means its memory space is a copy of the parent's.
Now if the child process…
Mohammed Arshaan
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2
votes
1 answer
Problem with cache and memory from university class
In my university class, I received this homework assignment on computer architecture, but I don't know how to solve it. I already know that the correct answer is 0, but I don't understand why. Could someone help me?
Problem:
The byte-addressable…
H0t_blue_B0i
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2
votes
1 answer
Assosciative mapping algorithm
I have been studying the assosciative mapping in a cache.Every line in a cache has a unique address which is made of:the index and the offset bits which give the the cache set and the cache line and the tag bits.But which algorithm really decides…
Cerise
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2
votes
2 answers
Resolving a dependency graph with insufficient resources to store all states
A common way to resolve a dependency graph is to compute an execution order, and then execute each stage in turn - storing and fetching the resources as necessary. In this example, when executing stage E we know that stage B is present in the cache…
sdfgeoff
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2
votes
1 answer
How does software prefetching work with in order processors?
From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching:
for (i = 0; i < N, i++) {
__prefetch(a[i + 8]);
__prefetch(b[i + 8]);
sum += a[i] * b[i];
}
On Wikipedia, it says that to determine the…
Rufat Imanov
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2
votes
1 answer
Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?
A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to Wikipedia are...
Providing a cache between the CPU and…
user133064
2
votes
1 answer
Byte addressable vs Word addressable
I am trying to understand the difference between byte addressing and word addressing.
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical…
avistein
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vote
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Does cache hit time include both time to read a cache and time to write a cache?
For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data cache?
LuminousStar
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1
vote
0 answers
How to decide row / column strides for a loop over a matrix get these cache hit rates?
Given CPU with:
L1 cache: 4-ways, block size = 32 bytes , cache size = 64KB , LRU (Cache replacement policy).
L2 cache: 2-ways, block size = 32 bytes , cache size = 512KB , LRU (Cache replacement policy).
Array: int32_t A[2048][128]; so element size…
JobProcessTask
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1
vote
2 answers
RAM access time vs cycle time
About Random Access Memory (SRAM and DRAM), if multiple read or write operation take place, many books calculate the average access time of those operations. Given the definition of access time, I think that it is wrong to talk about access time. If…
Bender
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How to determine the bits of the address used to access the cache?
Given a non-associative, direct-mapped cache and its cache capacity, block size, and address size, how would I go about determining what bits of the address are used to access to cache? Is there a generalized formula?
If there is a generalized…
Adam Lee
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vote
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Optimal order to traverse a grid with caching
Let's say I want to evaluate a two-argument function using all possible combinations of elements from sets A and B as arguments.
For example, if the function is addition, we get this grid:
A
1 2 3
1 2 3 4
B 2 3 4 5
3 4 5…
chpatrick
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vote
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Source code or detailed explanation of "WKS" virtual memory compression algorithm?
I've been trying to find information on various program data virtual memory compression algorithms that are in the "WK" family of algorithms. So far, I've been successful with the "WKdm" compression algorithm ( see here and here ). The other…
jdb2
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