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EDIT: This is not a duplicate - in the supposed duplicate there is no mention of sub/add instructions - only MOV. Thanks to harold for the helpful replies...

I know that the mov instruction using partial registers, such as eax, will clear the upper bits of the rax register.

However this also seems to happen for add/sub,

mov rcx, 1234567800000000h 

sub ecx,1

does not yield 12345678FFFFFFFFh for rax but 00000000FFFFFFFFh.

Same happens with add

mov rcx,12345678FFFFFFFFh

add ecx,1

Result is 0.

tinmanjk
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    This affects every write to a 32bit general purpose register (with an arguable caveat but whatever) – harold Mar 21 '21 at 02:07
  • well if there is not a overflow (carry flag style) it won't: mov rcx,1234567800000000h add rcx,0ABABABABh – tinmanjk Mar 21 '21 at 02:15
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    But that's a write to a 64bit register (`rcx`), so the whole story doesn't apply in that case – harold Mar 21 '21 at 02:17
  • you are right, sorry. Thanks for the reply! I am making the mistake of reading the Irvine book on Assembly Language where this is not emphasized (as in the original question in stackoverflow...) even the wrong answer is given in the section_review. Thanks again. – tinmanjk Mar 21 '21 at 02:22
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    IMO it is a duplicate; the quote from the Intel manual explains that this is expected, and the answer explains why that design decision makes sense. (The benefit is for instructions with a write-only destination, like `lea`, `mov`, the EDX output of `mul r/m32`, the destination of `imul ecx, edx, 123`, etc. Having RMW instructions like `add ecx, edx` behave differently from write-only instructions like `lea ecx, [rcx+rdx]` would be weird.) – Peter Cordes Mar 21 '21 at 02:28
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    @tinmanjk The duplicates are correct. This behaviour affects all 32 bit instructions. The duplicates even say so. – fuz Mar 21 '21 at 14:06
  • it is a duplicate if you look at the replies and not the top rated answers. – tinmanjk Mar 22 '21 at 22:59

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