Why can make work here?

Question

Makefile:

KERNEL_DIR := /usr/src/linux-2.6.32.9

obj-m := try.o

driver:     try.c
    make -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
clean:
    rm -rf *.o *.ko *.mod.c

When I type make,make -C $(KERNEL_DIR) SUBDIRS=pwdmodules is run,as if make driver is run ,why?

jho · Accepted Answer · 2011-03-22T08:15:58.667

3

make runs the first possible thing from a makefile if called without an argument. obj-m and KERNEL_DIR are not rules, they are variables. driver is the first rule to follow.

edited Mar 22 '11 at 08:15

answered Mar 22 '11 at 07:53

jho

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But in `driver` there's no `try.o`,how? – assem Mar 22 '11 at 08:00
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`obj-m` (and `KERNEL_DIR`) are not targets, but variables. `driver` is the first target and hence executed by make, if no concrete target is given on invocation – Lars Noschinski Mar 22 '11 at 08:12
What's the `try.c` behind target `driver` for? – assem Mar 22 '11 at 08:16
@assem: It's a dependency. It means that `driver` uses `try.c`, and if `try.c` has been modified from the last time you called `make`, `driver` will be rebuilt. – jho Mar 22 '11 at 08:20
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Isn't dependency specified by `:=`,not `:` ? – assem Mar 22 '11 at 08:25
@assem: They are both dependency declarations with a bit different meanings. http://stackoverflow.com/questions/448910/makefile-variable-assignment – jho Mar 22 '11 at 08:28
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There's a bit of confusion going on here. @jho: No, `:=` and `:` are not both dependency declarations; only the last one is. The first one is a variable assignment, similar to `=`; to read about the difference see the [GNU make manual (paragraph 6.2)](http://www.gnu.org/software/make/manual/make.html#Flavors). @assem: A single colon (`:`) separates a target and its dependencies. – eriktous Mar 22 '11 at 13:36
@eriktous, what about `make -C $(KERNEL_DIR) SUBDIRS=`pwd` modules`,why it doesn't take any parameters? – assem Mar 23 '11 at 01:51
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@assem: I don't understand your question. What do you mean by "it doesn't take any parameters"? This is just a command that runs make in the directory `$(KERNEL_DIR)`, with the variable `SUBDIRS` set to the current directory, and instructs make to build the target `modules`. There should be a Makefile in the directory `$(KERNEL_DIR)` which contains a rule that describes how to update `modules`. – eriktous Mar 23 '11 at 13:10

score 1 · Answer 2 · answered Mar 22 '11 at 08:12

1

If make is invoked without specifying a goal, make chooses the first target in the makefile as a goal. In this cases, it is driver. obj-m and KERNEL_DIR are only variable assignments, not targets.

answered Mar 22 '11 at 08:12

Lars Noschinski

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Can you talk about what exactly happened for `make driver` ? – assem Mar 22 '11 at 08:34

Why can make work here?

2 Answers2