What is the difference between = and <= in Verilog?

Question

What is the difference between = and <= in this code? Also, how do I print the value of data?

    module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end
// if i put     $print("data=%d", data);   there is error
endmodule

Possible duplicate of [How to interpret blocking vs non blocking assignments in Verilog?](http://stackoverflow.com/questions/4653284/how-to-interpret-blocking-vs-non-blocking-assignments-in-verilog) — Greg, Mar 24 '16 at 22:32
@Greg It is duplicate only if one already knows what `=` and `<=` mean. — Petr Gladkikh, Feb 16 '20 at 22:55

score 35 · Answer 1 · answered Feb 17 '16 at 06:09

35

= is blocking statement. In an always block, the line of code will be executed only after it's previous line has executed. Hence, they happens one after the other, just like combinatoral logics in loop.

<= is non-blocking in nature. This means that in an always block, every line will be executed in parallel. Hence leading to implementation of sequential elements.

answered Feb 17 '16 at 06:09

Sourabh

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"every line will be executed in parallel. Hence leading to implementation of sequential elements". Could you explain this, I am even more confused. Shouldn't sequential components be serially executed? – subtleseeker Nov 23 '19 at 18:56

score 25 · Accepted Answer · answered Feb 16 '16 at 14:46

<= is a nonblocking assignment. It is used to describe sequential logic, like in your code example. Refer to IEEE Std 1800-2012, section 10.4.2 "Nonblocking procedural assignments".

= is for blocking assignments. It is used to describe combinational logic.

See also Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

You can use $display instead of $print to print the value of variables. See also IEEE Std 1800-2012, section 21.2 "Display system tasks".

What is the difference between = and <= in Verilog?

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