I am interested in circuits that reduce $2^n-1$ input bits into their sum, represented as an $n$ bit integers. For $n=2$, this is a full adder, which can be implemented with 5 gates of 2 inputs in various ways. Alternatively, it can be directly implemented using 2 gates of 3 inputs (a parity gate and a majority gate).
For other values of $n$, what are the circuits with lowest gate counts to implement this reduction operation? I am in particular interested in $n=3$ and $n=4$ and implementations that make use of 2 input gates as well as implementations based on 3 input gates.
The obvious approach is to build a bunch of full adders of course, which e.g. comes out at 11 full adders for $n=4$, giving 55 2-input gates or 22 3-input gates.
Some general literature pointers are be appreciated, too.
